Unim Innovation Technology (Wuxi) Co.,Ltd.

Benefits

1. Social insurance and housing fund.
2. Annual health check and supplementary medical insurance, annual leave and additional paid leave.
4. Team building, welfare, birthday celebration.
5. Performance awards and stock options.
6. Training and promotion opportunities.
7. Free staff dormitory (Wuxi)
8. Gym and recreation area (Wuxi and Shanghai office)
9.Complimentary breakfast, afternoon tea, fruit of the day

Job Search

Please submit your resume to our HR, email: hr@unimcom.com

Position Location Department View

Layout engineer Social Recruitment,Shanghai Research and Development: Work City
ShangHai

Job Responsibilities:
1. Provide the overall design requirements of chips and modules and complete the Floorplan;Complete block level and Top level layout design according to design rules and circuit requirements
2. Completed module and chip layout design verification, including LVS, DRC, ANTENNA, PERC, etc
3. Generate Abstract and LEF and other relevant documents
4. Extract parasitic parameters and assist circuit engineers to complete post-imitation
5. Assist APR engineer to complete SOC chip integration
6. Generate tape-out data and files
7. Write relevant layout documents

Qualifications:
1. Bachelor degree or above in microelectronics, electronic engineering or related field
2. At least 2 years analog and mixed signal layout working experience
3. Familiar with IC design process, and have some basic knowledge of semiconductor devices and analog circuit
4. Proficient in IC layout design and validation tools (Cadence, Calibre, etc.);Proficiency with Virtuoso-XL is a plus
5. Memory layout experience in Flash/SRAM/ROM is preferred
6. Familiar with SKILL/TCL and APR working experience is preferred

Senior CAD Engineer Social Recruitment,Shanghai Research and Development: Work City
ShangHai

Job Responsibilities:
1. Develop and maintain intensive models of non-volatile memory, develop and maintain physical validation tools (DRC, LVS and parasitic parameter extraction) to support product development of non-volatile memory;
2. Develop and support the company's internal analog or digital design process, use scripting language to develop in House scripts and tools to provide design efficiency;
3. Design Rule verification (DRC) tool development process based on Calibre SVRF or equivalent;
4. Development process of LVS tools based on IC Validator, Calibre SVRF or equivalent;
5. Development process of PEX tool based on StarRC or Calibre nmxRC;
6. Development of design automation and management tools based on Cadence SKILL programming language and CDF interface, and their integrated interaction with Virtuoso process database, schematic editor, layout editor, design data translator, analog and digital Circuit design environment (ADE);

Qualifications:
1. Bachelor degree or above in electrical engineering, electronic engineering, micro-electronic engineering, computer Science, applied physics, material science or applied mathematics
2. Good English writing and oral communication skills
3. Familiar with Cadence Virtuoso/Mentor Calibre/Synopsys and other tools and design processes
Proficient in at least one modern programming language (e.g., Fortran, C, C++, C#, Java, etc.)
5. Familiar with Linux, FreeBSD or Unix
6. Proficient in at least one circuit simulator (e.g., HSPICE, Spectre, Eldo, PSPICE, PowerSPICE, Alps, SmartSPICE, etc.) and able to work at netlist level.Proficient in at least one IC layout editing software (e.g., KLayout, Virtuoso, Laker, L-Edit, Pyxis, Aether, GYM, etc.